Generally, the minimum feature size fabricated in a particular semiconductor process is an objective measure that indicates how advanced, and how complex, that process is. Currently integrated circuits manufacturers may fabricate silicon integrated circuits using 65 nanometer (sometimes “65 nm”) minimum feature size processes and are transitioning to 45 nanometers (“45 nm”) processes in the immediate future, further advances will lead to processes with even smaller minimum feature sizes. Smaller minimum feature sizes increase the density of devices, increase the number of devices that may be incorporated into a single die, increase the switching speeds of the transistors and thus the performance of the integrated circuits produced using the process, and may increase the number of integrated circuits that can be produced on a single semiconductor wafer, thus lowering manufacturing costs and making increased performance possible at the same time.
One disadvantage of the prior art semiconductor devices is that as the fabrication processes shrink in size, undesirably increased junction leakage currents may occur due to the geometric features of certain regions that are formed adjacent to, or in proximity to, each other during the manufacture of, for example, MOS semiconductor transistor devices, which includes P channel MOS and N channel MOS transistors. Various approaches to improving the leakage current performance of these devices have been proposed, but these known approaches typically require extra processing steps, and therefore add additional cost and complexity to the processing methods; including the need for additional photolithographic masks and repeated use of photoresist, etch, implant and photoresist strip steps to achieve the desired geometric shapes in the finished devices.
Further the process tolerances and manufacturing variations that occur during processing may cause slight misalignment in certain process steps. Sometimes this slight misalignment results in a contact structure made to a source or drain diffused region actually forming slightly out of alignment, or forming slightly deeper than intended, and thereby electrically and/or physically contacting or forming very near a junction boundary between a diffusion region and a well region, which can increase the leakage current of the fabricated device. As the processes continue to shrink in size, this kind of leakage current becomes more prevalent and the resulting leakage current degrades the performance of the finished integrated circuits below the expected performance, and may even cause finished devices to be scrapped, the misalignment then increasing the costs of production of the integrated circuits by lowering the yield of the process.
FIG. 1 depicts an illustration, not to scale, in cross sectional view, of a conventional MOS device depicting one of either a P or N channel MOS transistor 1 fabricated using present processing techniques.
In FIG. 1, a substrate 3 which may be doped to a P or N type as is known in the art, is provided. Retrograde well 10 is formed which has the doping needed to support a channel for the MOS transistor, e.g. for an N channel transistor, the well is a P type, for a P channel transistor, the well is an N type dopant. The well is often doped with slow diffusing ions for example indium for N type devices, and arsenic or antimony for P type devices.
Standard features for a MOS transistor are shown, a gate oxide 7 is formed from a thermally grown or CVD deposited oxide layer or sometimes an oxide and a nitride is used, conductive gate 9 which can be formed of a conductive material such as a polysilicon material is formed. The gate material is used in a self aligned process and lightly doped drain (LDD) regions 11 are formed by implanting the correct dopant species (boron for N channel devices, phosphorous for P channel devices) and following the implant with a thermal anneal or sometimes a rapid thermal anneal. Halo implants 13 are performed and again use the slow diffusing species appropriate for the type of MOS transistor being formed, these slow diffusing halo implants prevent out diffusion of the more mobile implanted ions in the lightly doped drain regions (sometimes called “LDD” or, source drain extensions, “SDE”) into the channel region by creating a guard region around and beneath the lightly doped drain. These implants may be performed at an acute angle to the vertical so that they can extend beneath the gate region.
Sidewall spacers 15 are formed on the gate polysilicon using conventional oxide and nitride deposition or thermal growth techniques. The sidewalls are then used during a second self aligned implant step to form the deeper source and drain diffused regions 17 using the appropriate dopant, boron or phosphorous, to complete the MOS transistor source and drain regions. Again slow or rapid thermal anneal steps may be used to drive and activate the dopants in the diffusion regions. Since the source and the drain of the transistor are symmetrical and which one is the source and which the drain is arbitrarily chosen based on the electrical connections made later, these regions are usually referred to simply as source/drain regions.
Following formation of the source/drain diffusion regions, a conductive metal such as titanium may be deposited over the diffusion regions to form a silicide, again a self aligned process is used, so that this is often referred to as a salicide layer, Layer 21 in FIG. 1 depicts the salicide regions which are formed over the polysilicon gate and the source and drain regions 17. Various known processes for forming the salicide 21 may be used. The formation of salicide over these regions results in a lower resistivity, improving performance of the finished transistor.
A contact etch stop layer (sometimes, CESL) 23 is applied over the structure to complete the intermediate structure for transistor 1 as shown in FIG. 1. This CESL layer 23 may also be used to apply physical stress or strain onto the channel region for the MOS device in order to increase carrier mobility and performance, as is known in the art. Shallow trench isolation (STI) regions 5 are shown and isolate the completed MOS transistor 1 from adjacent devices (not shown), also, as is known in the art, various other isolation methods such as field oxide regions may be used. The transistor 1 may be formed in a well first formed in a substrate, or, in an epitaxial layer formed over an insulator, such as an SOI structure, also as is known in the art.
FIG. 2 depicts the prior art transistor 1 of FIG. 1 in cross section after further process steps have been completed. In FIG. 2, an interlevel dielectric or isolation layer (sometimes referred to as ILO) 25 is formed over the CESL layer 23, this insulating layer may be formed of oxide or oxide and nitride layers as is known in the art. Interlevel dielectric layer 25 is subsequently patterned to form a via for a contact region which is then subsequently filled with a conductive material 29 to form contact over the source/drain region 17 and extending through the interlevel dielectric layer 25. A first level of metallization 27 is formed overlying the interlevel dielectric layer 25 and may be formed of aluminum or copper as is known in the art. This metallization layer overlies the top of and electrically contacts the contact 29 and forms an electrical connection to the source/drain region 17.
FIG. 2 also depicts the effects of misalignment as occurs in the prior art processing steps. Region 31 in FIG. 2 depicts the contact material extending almost through the lightly doped drain region 11 at a point near the boundary of the lightly doped drain 11 and the halo implant 13. In a more severe case, the contact material might extend completely through the lightly doped drain region. In any event, the contact 29 as shown in FIG. 2 is too near the boundary of the outer surface of the lightly doped drain diffusion region 11 with the halo implant 13, and thus junction leakage currents can flow from the source/drain contact 29 into the channel region, which is a failure caused by the misalignment. (Ideally, the contact 29 would end at or very near the surface of the source/drain region 17 and would not extend into the lightly doped drain region 11 as shown.)
FIG. 3 is a prior art drawing which depicts in cross section the region 31 and other features of the transistor 1 from FIG. 2 in a closer view, again this drawing is not to scale. The bottom and side edges of contact 29 are shown extending into the lightly doped drain region 11 and are formed very close to the outer boundary of the LDD region 11 and the well region where the halo implant 13 meets the LDD region. Again it can be seen that the contact 29 in this example is formed too near the LDD boundary. This proximity results in additional leakage current and correspondingly poor performance of the completed devices.
Certain prior art approaches to adding spacing in the gate sidewall area where the source/drain contacts are made adjacent a gate electrode sidewall are known. U.S. Pat. No. 6,207,519, to Kim et al., issued Mar. 27, 2001, describes a method of creating double sidewall spacers for a self aligned source contact in a MOS device by repeatedly performing implants, and anneals, growing a spacer on a sidewall of a gate electrode. Kim et al. provides additional spacing for the source contact away from the channel region. If this known process were applied to a CMOS device, it would require additional mask, photoresist, implant and strip steps for both the N-MOS and P-MOS transistors resulting in several additional processing steps. A second disadvantage of this approach is that the area used for each device is increased to increase the feature spacing, thus reducing the available silicon area (and therefore providing reduced device density). A similar approach is described in U.S. Pat. No. 6,165,880, to Yaung et al., which is assigned to the owner of the present application and which is herein incorporated by reference.
Additional engineering of the source/drain diffusions and the channel may be performed as is known in the prior art. The use of graded source drain junctions to reduce leakage current is known. U.S. Pat. No. 5,972,762, to Wu, issued Oct. 26, 1999, for example, describes the use of silicon recesses formed in the source drain regions adjacent a gate electrode to create a gradual source drain junction. The use of pocket implants, including angled implants, is known to create diffusions extending underneath the gate electrode or sidewalls, for example U.S. Patent Application Publication No. 2004/0063289A1, which published Apr. 1, 2004, describes angled implants to place dopants underneath sidewall spacers.
A continuing need exists thus for a MOS structure and fabrication methods for MOS devices to address the leakage current that results in prior art MOS transistors due to the proximity of the source/drain contact and the channel region. There is a need for a simple and economical way to reduce the leakage current and to increase the process tolerance of any misalignment that may occur in the manufacturing process. The methods and structures of the present invention address these needs.